Webinar on "VLSI Design using Verilog HDL"

Feb 7, 2020

The Department of Electrical and Electronics Engineering, NMAMIT, Nitte had organised a webinar on VLSI Design using Verilog HDL by Mr. P R Sivakumar, CEO, Maven Silicon VLSI Training Centre, Bangalore on 7 February, 2020 between 02:00 PM and 05:00 PM at NC22, Sir MV Block. 56 students and 02 faculty members attended the session. The session gave an in-depth knowledge on the Overview of VLSI Design, RTL Design using Verilog HDL, Data Types and Verilog Operators.



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